Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study (bibtex)
by Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
Reference:
Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler, "Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study", In Forum on specification & Design Languages (FDL), 2020.
Bibtex Entry:
@InProceedings{HGJD:2020,
  title         = {Efficient Cross-Level Testing for Processor Verification: A {RISC-V} Case-Study},
  author        = {Vladimir Herdt and Daniel Gro{\ss}e and Eyck Jentzsch and Rolf Drechsler},
  booktitle     = {Forum on specification & Design Languages (FDL)},
  year		= {2020},
  mycomment     = {(Best Paper Award)},
  keywords={easecrc_cognitive_arch_systems}
}
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